<< Click to Display Table of Contents >> Navigation: AutoTRAX PCB Design Express (DEX) > Designs > Circuit Simulation > The Spice Reference Manual > Circuit Description > Circuit Elements and Models > Transistors and Diodes > MOSFET Models (NMOS/PMOS) 
SPICE provides four MOSFET device models, which differ in the formulation of the IV characteristic. The variable LEVEL specifies the model to be used:
LEVEL=1 > ShichmanHodges
LEVEL=2 > MOS2 (as described in [1])
LEVEL=3 > MOS3, a semiempirical model(see [1])
LEVEL=4 > BSIM (as described in [3])
LEVEL=5 > new BSIM (BSIM2; as described in [5])
LEVEL=6 > MOS6 (as described in [2])The dc characteristics of the level 1
through level 3 MOSFETs are defined by the device parameters VTO, KP, LAMBDA, PHI and GAMMA. These parameters are computed by SPICE if process parameters (NSUB, TOX, ...) are given, but userspecified values always override. VTO is positive (negative) for enhancement mode and negative (positive) for depletion mode Nchannel (Pchannel) devices. Charge storage is modeled by three constant capacitors, CGSO, CGDO, and CGBO which represent overlap capacitances, by the nonlinear thinoxide capacitance which is distributed among the gate, source, drain, and bulk regions, and by the nonlinear depletionlayer capacitances for both substrate junctions divided into bottom and periphery, which vary as the MJ and MJSW power of junction voltage respectively, and are determined by the parameters CBD, CBS, CJ, CJSW, MJ, MJSW and PB. Charge storage effects are modeled by the piecewise linear voltagesdependent capacitance model proposed by Meyer. The thinoxide chargestorage effects are treated slightly different for the LEVEL=1 model. These voltagedependent capacitances are included only if TOX is specified in the input description and they are represented using Meyer's formulation.
There is some overlap among the parameters describing the junctions, e.g. the reverse current can be input either as IS (in A) or as JS (in A/m2). Whereas the first is an absolute value the second is multiplied by AD and AS to give the reverse current of the drain and source junctions respectively. This methodology has been chosen since there is no sense in relating always junction characteristics with AD and AS entered on the device line; the areas can be defaulted. The same idea applies also to the zerobias junction capacitances CBD and CBS (in F) on one hand, and CJ (in F/m2) on the other. The parasitic drain and source series resistance can be expressed as either RD and RS (in ohms) or RSH (in ohms/sq.), the latter being multiplied by the number of squares NRD and NRS input on the device line.
A discontinuity in the MOS level 3 model with respect to the KAPPA parameter has been detected (see [10]). The supplied fix has been implemented in Spice3f2 and later. Since this fix may affect parameter fitting, the option "BADMOS3" may be set to use the old implementation (see the section on simulation variables and the ".OPTIONS" line).
SPICE level 1, 2, 3 and 6 parameters:
name 
parameter 
units 
default 
example 
LEVEL 
model 
 
1 

VTO 
zerobias threshold voltage (VT0) 
V 
0 
1 
KP 
transconductance parameter 
A/V2 
2.0e5 
3.1e5 
GAMMA 
bulk threshold parameter ( ) 
V1/2 
0 
0.37 
PHI 
surface potential ( ) 
V 
0.6 
0.65 
LAMBDA 
channellength modulation (MOS1 and MOS2 only) ( ) 
1/V 
0 
0.02 
RD 
drain ohmic resistance 
Ohm 
0 
1 
RS 
source ohmic resistance 
Ohm 
0 
1 
CBD 
zerobias BD junction capacitance 
F 
0 
20fF 
CBS 
zerobias BS junction capacitance 
F 
0 
20fF 
IS 
bulk junction saturation current (IS) 
A 
1.oe14 
1.0e15 
PB 
bulk junction potential 
V 
0.8 
0.87 
CGSO 
gatesource overlap capacitance per meter channel width 
F/m 
0 
4.0e11 
CGDO 
gatedrain overlap capacitance per meter channel width 
F/m 
0 
4.0e11 
CGBO 
gatebulk overlap capacitance per meter channel length 
F/m 
0 
2e1 
RSH 
drain and source diffusion sheet resistance 
Ohm/square 
0 
10 
CJ 
zerobias bulk junction bottom cap. per sqmeter of junction area 
F/m2 
0 
2.0e4 
MJ 
bulk junction bottom grading coeff. 
 
0.5 
0.5 
CJSW 
zerobias bulk junction sidewall cap. per meter of junction perimeter 
F/m 
10 
1.0e9 
MJSWE 
bulk junction sidewall grading coeff. 
 
0.5 (level1) 0.33(level 2,3) 

FS 
bulk junction saturation current per sqmeter of junction area 
A/m2 

1.0e8 
TOX 
oxide thickness 
meter 
1.0e7 
1.0e7 
NSUB 
substrate doping 
1/cm3 
0 
4.0e15 
NSS 
surface state density 
1/cm2 
0 
1.0e10 
NFS 
fast surface state density 
1/cm2 
0 
1.0e10 
TPG 
type of gate material: +1 opp. to substrate 1 same as substrate 0 Al gate 
 
1.0 

XJ 
metallurgical junction depth 
meter 
0 
1 micron 
LD 
lateral diffusion 
meter 
0 
0.8 micron 
UO 
surface mobility 
cm2/Vs 
600 
700 
UCRIT 
critical field for mobility degradation (MOS2 only 
V/cm 
600 
1.0e4 
UEXP 
critical field exponent in mobility degradation (MOS2 only) 
 
1.0e04 
0.1 
UTRA 
transverse field coeff. (mobility) (deleted for MOS2) 
 
0 
0.3 
VMAX 
maximum drift velocity of carriers 
m/s 
0 
5.0e40.3 
NEFF 
total channelcharge (fixed and mobile) coefficient (MOS2 only 
 
0 
5.0 
KF 
flicker noise exponent 
 
0 
1.0e26 
AF 
flicker noise exponent 
 
1 
1.2 
FC 
coefficient for forwardbias depletion capacitance formula 
 
0.5 

DELTA 
width effect on threshold voltage (MOS2 and MOS3) 
 
0 
1.0 
THETA 
mobility modulation (MOS3 only 
1/V 
0 
0.1 
ETA 
static feedback (MOS3 only) 
 
0 
1.0 
KAPPA 
saturation field factor (MOS3 only) 
 
0.2 
0.5 
TNOM 
parameter measurement temperature 
ºC 
25 
50 
The level 4 and level 5 (BSIM1 and BSIM2) parameters are all values obtained from process characterization, and can be generated automatically. J. Pierret [4] describes a means of generating a 'process' file, and the program Proc2Mod provided with SPICE3 converts this file into a sequence of BSIM1 ".MODEL" lines suitable for inclusion in a SPICE input file. Parameters marked below with an * in the l/w column also have corresponding parameters with a length and width dependency. For example, VFB is the basic parameter with units of Volts, and LVFB and WVFB also exist and have units of Volt meter The formula
is used to evaluate the parameter for the actual device specified with
and
Note that unlike the other models in SPICE, the BSIM model is designed for use with a process characterization system that provides all the parameters, thus there are no defaults for the parameters, and leaving one out is considered an error. For an example set of parameters and the format of a process file, see the SPICE2 implementation notes[3].
For more information on BSIM2, see reference [5].
SPICE BSIM (level 4) parameters:
name 
parameter 
units 
1/w 
VFB 
flatband voltage 
V 
* 
PHI 
surface inversion potential 
V 
* 
K1 
body effect coefficient 
V1/2 
* 
K2 
drain/source depletion chargesharing coefficient 
 
* 
ETA 
zerobias draininduced barrierlowering coefficient 
 
* 
MUZ 
zerobias mobility 
cm2/Vs 

DL 
shortening of channel 
micron 

DW 
narrowing of channel 
micron 

U0 
zerobias transversefield mobility degradation coefficient 
V1 
* 
U1 
zerobias velocity saturation coefficient 
micron/V 
* 
X2MZ 
sens. of mobility to substrate bias at vds=0 
cm2/Vs 
* 
X2E 
sens. of draininduced barrier lowering effect to substrate bias 
V1 
* 
X3E 
sens. of draininduced barrier lowering effect to drain bias at Vds=Vdd 
V1 
* 
X2U0 
sens. of transverse field mobility degradation effect to substrate bias 
V2 
* 
X2U1 
sens. of velocity saturation effect to substrate bias 
micron/V2 
* 
MUS 
mobility at zero substrate bias and at Vds=Vdd 
cm2/Vs 

X2MS 
sens. of mobility to substrate bias at Vds=Vdd 
cm2/Vs 
* 
X3MS 
sens. of mobility to drain bias at Vds=Vdd 
cm2/Vs 
* 
X3U1 
sens. of velocity saturation effect on drain bias at Vds=Vdd 
cm2/Vs 
* 
TOX 
TOX 	gate oxide thickness 
micron 

TEMP 
temperature at which parameters were measured 
ºC 

VDD 
measurement bias range 
V 

CGD0 
gatedrain overlap capacitance per meter channel width 
F/m 

CGSO 
gatesource overlap capacitance per meter channel width 
F/m 

CGBO 
gatebulk overlap capacitance per meter channel length 
F/m 

XPART 
gateoxide capacitancecharge model flag 
 
* 
NO 
zerobias subthreshold slope coefficient 
 
* 
NB 
sens. of subthreshold slope to substrate bias 
 
* 
ND 
sens. of subthreshold slope to drain bias 
 

RSH 
drain and source diffusion sheet resistance 
Ohm/square 

JS 
source drain junction current density 
A/m2 

PB 
built in potential of source drain junction 
V 

MJ 
Grading coefficient of source drain junction 
 

PBSW 
built in potential of source, drain junction sidewall 
V 

MJSW 
grading coefficient of source drain junction sidewall 
 

CJ 
Source drain junction capacitance per unit area 
F/m2 

CJSW 
source drain junction sidewall capacitance per unit length 
F/m 

WDF 
source drain junction default width 
m 

DELL 
Source drain junction length reduction 
m 

XPART = 0 selects a 40/60 drain/source charge partition in saturation, while XPART=1 selects a 0/100 drain/source charge partition.
ND, NG, and NS are the drain, gate, and source nodes, respectively. MNAME is the model name, AREA is the area factor, and OFF indicates an (optional) initial condition on the device for dc analysis. If the area factor is omitted, a value of 1.0 is assumed. The (optional) initial condition specification, using IC=VDS, VGS is intended for use with the UIC option on the .TRAN control line, when a transient analysis is desired starting from other than the quiescent operating point. See the .IC control line for a better way to set initial conditions.